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| RFP12N10L Data Sheet January 2002 12A, 100V, 0.200 Ohm, Logic Level, N-Channel Power MOSFET These are N-Channel enhancement mode silicon gate power field effect transistors specifically designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching and solenoid drivers. This performance is accomplished through a special gate oxide design which provides full rated conduction at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. Formerly developmental type TA09526. Features * 12A, 100V * rDS(ON) = 0.200 * Design Optimized for 5V Gate Drives * Can be Driven Directly from QMOS, NMOS, TTL Circuits * Compatible with Automotive Drive Requirements * SOA is Power-Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance Ordering Information PART NUMBER RFP12N10L PACKAGE TO-220AB BRAND F12N10L * Majority Carrier Device * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards NOTE: When ordering, include the entire part number. Symbol D G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (TAB) (c)2002 Fairchild Semiconductor Corporation RFP12N10L Rev. B RFP12N10L Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFP12N10L Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 1M) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Above TC = 25oC, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 100 100 12 30 10 60 0.48 -55 to 150 300 260 UNITS V V A A V W W/oC oC oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250mA, VGS = 0V VGS = VDS, ID = 250mA (Figure 7) VDS = 65V, VDS = 80V VDS = 65V, VDS = 80V TC = 125oC MIN 100 1 ID = 6A, VDD = 50V, RG = 6.25, VGS = 5V (Figures 9, 10, 11) RFP12N10L TYP 15 70 100 80 MAX 2 1 50 100 0.2 900 325 170 50 150 130 150 2.083 UNITS V V A A A pF pF pF ns ns ns ns oC/W Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Input Capacitance Output Capacitance Reverse-Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Thermal Resistance Junction to Case IGSS rDS(ON) CISS COSS CRSS td(ON) tr td(OFF) tf RJC VGS = 10V, VDS = 0V ID = 12A, VGS = 5V (Figures 5, 6) VGS = 0V, VDS = 25V, f = 1MHz (Figure 8) Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time NOTES: 2. Pulsed: pulse duration = 80s max, duty cycle = 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. SYMBOL VSD trr ISD = 6A ISD = 4A, dISD/dt = 50A/s TEST CONDITIONS MIN TYP 150 MAX 1.4 UNITS V ns (c)2002 Fairchild Semiconductor Corporation RFP12N10L Rev. B RFP12N10L Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 10 DC OPERATION Unless Otherwise Specified 100 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) ID(MAX) CONTINUOUS TC = 25oC TJ = MAX RATED 0.8 0.6 0.4 0.2 0 1 60W 0 50 100 150 TC, CASE TEMPERATURE (oC) 0.1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 1000 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. FORWARD BIAS OPERATING AREA 40 ID(ON), ON-STATE DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE 0.5% TC = 25oC ID, DRAIN CURRENT (A) 30 20 VDS = 10V PULSE DURATION = 80s DUTY CYCLE 0.5% 15 25oC 10 125oC 5 125oC 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 0 1 2 -40oC VGS 5V = 10 V 20 4V 10 3V 2V -40oC 3 4 5 0 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 3. SATURATION CHARACTERISTICS FIGURE 4. TRANSFER CHARACTERISTICS 0.3 NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE () 125oC 2.0 VGS = 5V, ID = 12A PULSE DURATION = 80s DUTY CYCLE 0.5% 1.5 0.2 25oC -40oC 1.0 0.1 VGS = 5V PULSE DURATION = 80s DUTY CYCLE 0.5% 0 0 5 10 15 20 ID, DRAIN CURRENT (A) 25 30 0.5 0 -50 0 50 100 TJ, JUNCTION TEMPERATURE (oC) 150 FIGURE 5. DRAIN TO SOURCE ON RESISTANCE vs DRAIN CURRENT FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE (c)2002 Fairchild Semiconductor Corporation RFP12N10L Rev. B RFP12N10L Typical Performance Curves 1.3 1.2 THRESHOLD VOLTAGE (V) NORMALIZED GATE 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -50 0 50 100 150 0 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) 50 VDS = VGS ID = 250A C, CAPACITANCE (pF) 600 Unless Otherwise Specified (Continued) 800 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD CISS 400 200 COSS CRSS TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 100 DRAIN TO SOURCE VOLTAGE (V) BVDSS RL = 8.33 IG (REF) = 0.56mA VGS = 5V FIGURE 8. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 GATE TO SOURCE VOLTAGE (V) 8 75 GATE VDD = BVDSS SOURCE V = BVDSS VOLTAGE DD 50 6 4 25 0.75BVDSS 0.50BVDSS 0.25BVDSS DRAIN SOURCE VOLTAGE 20 IG (REF) IG (ACT) t, TIME (s) 80 IG (REF) IG (ACT) 2 0 0 NOTE: Refer to Fairchild Applications Notes AN7254 and AN7260 FIGURE 9. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 10. SWITCHING TIME TEST CIRCUIT FIGURE 11. RESISTIVE SWITCHING WAVEFORMS (c)2002 Fairchild Semiconductor Corporation RFP12N10L Rev. B RFP12N10L Test Circuits and Waveforms (Continued) VDS RL VDD VDS VGS = 10V VGS + Qg(TOT) Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IG(REF) 0 VGS = 5V DUT IG(REF) FIGURE 12. GATE CHARGE TEST CIRCUIT FIGURE 13. GATE CHARGE WAVEFORMS (c)2002 Fairchild Semiconductor Corporation RFP12N10L Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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